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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "06/12/2023 17:16:54"
                                                                                
// Verilog Test Bench template for design : LCD_On_FPGA
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ps
module LCD_On_FPGA_tb();
// constants                                           
// general purpose registers
//reg eachvec;
// test vector input registers
reg clk;
reg reset_n;
// wires                                               
wire tft_csx;
wire [15:0]  tft_d_inout;
wire tft_dcx;
wire tft_rdx;
wire tft_reset_n;
wire tft_wrx;
wire [7:0]SEL;
wire [7:0]DIG;
wire tft_bl;


always #10 clk = ~clk;

initial begin
        #0 clk = 1'b0;
		  #0 reset_n = 1'b1; #61 reset_n = 1'b0; #20 reset_n = 1'b1;
        end






// assign statements (if any)                          
top i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.reset_n(reset_n),
	.tft_csx(tft_csx),
	.tft_d_inout(tft_d_inout),
	.tft_dcx(tft_dcx),
	.tft_rdx(tft_rdx),
	.tft_reset_n(tft_reset_n),
	.tft_wrx(tft_wrx),
	.DIG(DIG),
	.SEL(SEL),
	.tft_bl(tft_bl)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
                                           
endmodule

